KIM-I Hardware Manual V1.0

Publications Number 6500-10A MCS6500 MICROCOMPUTER FAMILY HARDWARE MANUAL JANUARY 1976 The information in this manual has been reviewed and is believed to be entirely reliable. However, no responsibility is assumed for inaccuracies. The material in this manual is for informational purposes only and is subject to change without notice. Second Edition © MOS TECHNOLOGY, INC. 1976 "All Rights Reserved" MOS TECHNOLOGY, INC. 950 Rittenhouse Road Norristown, PA 19401 Revision A PREFACE The MOS Technology, Inc. MGS6500 Microcomputer System offering combines the best features of second generation families into a product line that is both a price and performance leader. A growing array of products and a unique micro- processor family provide the customer with answers to the complex design prob- lems confronting today's programmers and designers. Integrated circuit fabrication techniques have moved microprocessors to the forefront of complex, sophisticated components. The MCS6500 family benefits from an advanced but proven process technology; N-Channel, Silicon Gate, and De- pletion Loads are the key elements providing the high performance character- istics obtainable in the single supply 5-volt system usage of the MCS6500 family. The N-Channel, Silicon Gate technology is enhanced by use of Depletion Loads which provides greater speed, lower power and smaller chip size than previous processing approaches. Ion Implementation techniques are basic elements in pro- viding control and stability of all processing parameters necessary to achieve the electrical characteristics of the MCS6500 product line. These character- istics provide a price/performance combination which establishes the MCS6500 family as the product offering best meeting the economic and technical demands of today's system designs. A word of explanation is in order regarding the MCS6500 product line, since the concept of "Microprocessor Family" is indeed unique to the industry. It is helpful to understand the basic product structure of the MCS6500 family. The MCS650X Series represents the Microprocessor Family. Within this family will exist a series of 8-bit devices offering a wide range of options and capabilities for the customer. For the single-application customer, a varied selection of devices is at his disposal in choosing the one that best meets his specific needs. The "Microprocessor Family" concept has an even greater impact -ii- to the user who has a variety of applications, each of which can best be served by a specific member of the family. It is important to this user that all of the different microprocessors he selects maintain compatibility--both hardware (from the standpoint of bus and electrical specifications) and software. The MCS650X product line is the first microprocessor family to achieve such a level of compatibility because it was indeed conceptualized as a totally software and hardware compatible family of microprocessors offering a range of performance options from which the designer can select. The MCS6501 and MCS6502 are the first two 40-pin members of the MCS650X family, each offering 65K bytes of addressable memory. The MCS6503, MCS6504 and MCS6505 are the first 28-pin versions with various options of addressing capability and control functions from which to choose. The MCS652X Series represents Peripheral Input/Output devices, the first being the MCS652O which is a direct replacement for the Motorola MC682O Periph- eral Interface Adapter (PIA). Subsequent members of this series will include devices with expanded I/O capabilities. The MCS653X Series represents combinational devices--those consisting of various tradeoffs in RAM, ROM, I/O, and Timing. The first of these is the MCS6530 which contains 1K bytes of ROM, 64 bytes of RAM, an Interval Timer and 16 I/O lines. Subsequent products in this series will provide the customer with different combinations and new implementations of I/O, Timing and Memory. The MCS654X Series represents Read Only Memories specifically tailored to meet the needs of large program storage required in many of the applications of the MCS6500 family of products. The first of these will be a 16K (2K x 8) ROM, the MCS6540. All of the MCS6500 product lines outlined utilize the same fabrication techniques and meet identical electrical specifications. With this family of compatible products the designer of today has at his disposal the elements necessary to develop a system configured to meet the most demanding tasks. Complementing the MCS6500 family is a selection of Random Access Memories totally compatible with the microcomputer family. The first of these will be the MCS6102, a 2102 equivalent, and the MCS6111, a 2111 equivalent. To allow for minimum I/O cost and maximum user flexibility, all of the MCS6500 products are compatible with the M6800 bus structure. -iii- Chapter 1 of this manual introduces the reader to the MCS6500 Microcomputer System. It includes an introduction to terminology, an explanation of system components of a general microcomputer system, and then discusses the components of the MCS6500 Product Family. Chapter 2 is applications-oriented, with a discussion of system configura- tion, the I/O port, handshaking and specific examples on interrupt prioritizing, interfacing with peripherals, direct memory addressing techniques, and control of memories in the system. Chapter 3 is directed at the important task of bringing up a system. It takes the reader trough a step-by-step procedure in analyzing, statically and dynamically, the basic elements of the system to assist the user in a smooth transition from a conceptual system to an operational one. -iv- TABLE OF CONTENTS CHAPTER 1 THE MCS6500 MICROCOMPUTER SYSTEM 1.0 Designing with Microcomputer Systems. . . . . . . . . . . . . . 3 1.1 Introduction to Microcomputer Systems . . . . . . . . . . . . . 4 1.1.1 Organization of a Microcomputer System. . . . . . . . . . . . 4 1.1.2 Basic Operation . . . . . . . . . . . . . . . . . . . . . . . 4 1.1.3 Addressing Terms and Concepts . . . . . . . . . . . . . . . . 4 1.1.3.1 Bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 1.1.3.2 Address Space . . . . . . . . . . . . . . . . . . . . . . . 6 1.1.3.3 The Address Page. . . . . . . . . . . . . . . . . . . . . . 6 1.1.4 System Components . . . . . . . . . . . . . . . . . . . . . . 8 1.1.4.1 Clock Generator . . . . . . . . . . . . . . . . . . . . . . 8 1.1.4.2 Program Memory. . . . . . . . . . . . . . . . . . . . . . . 8 1.1.4.3 Data Memory . . . . . . . . . . . . . . . . . . . . . . . . 9 1.1.4.4 Input/Output Devices. . . . . . . . . . . . . . . . . . . 10 1.1.4.5 The Microprocessor. . . . . . . . . . . . . . . . . . . . 10 1.2 Introduction to the MCS650X Microprocessor Family . . . . . . 12 1.2.1 The MCS6501 . . . . . . . . . . . . . . . . . . . . . . . . 12 1.2.2 The MCS6502 . . . . . . . . . . . . . . . . . . . . . . . . 14 1.2.3 The MCS6503, MCS6504 and MCS6505. . . . . . . . . . . . . . 14 1.3 MCS6500 System Concepts . . . . . . . . . . . . . . . . . . . 15 1.3.1 Bus Structure . . . . . . . . . . . . . . . . . . . . . . . 15 1.3.2 Processor Interrupts. . . . . . . . . . . . . . . . . . . . 16 1.3.2.1 Applications for Interrupts . . . . . . . . . . . . . . . 20 1.3.2.2 Interrupt Prioritizing. . . . . . . . . . . . . . . . . . 22 1.3.2.3 System Interconnect for Interrupts. . . . . . . . . . . . 22 1.3.2.4 Interrupt Servicing . . . . . . . . . . . . . . . . . . . 23 1.3.2.5 Interrupt Request (IRQ) . . . . . . . . . . . . . . . . . 25 1.3.2.6 Non-Maskable Interrupt (NMI-) . . . . . . . . . . . . . . 27 1.3.3 System Reset. . . . . . . . . . . . . . . . . . . . . . . . 27 -v- 1.4 The Microprocessors . . . . . . . . . . . . . . . . . . . . . 30 1.4.1 The MCS650l . . . . . . . . . . . . . . . . . . . . . . . . 30 1.4.1.1 Introduction. . . . . . . . . . . . . . . . . . . . . . . 30 1.4.1.2 The MCS6501 Pinouts . . . . . . . . . . . . . . . . . . . 32 1.4.1.2.1 Vcc, Vss--Supply Lines. . . . . . . . . . . . . . . . . 32 1.4.1.2.2 AB00 - AB15--Address Bus. . . . . . . . . . . . . . . . 32 1.4.1.2.3 DB0 - DB7--Data Bus . . . . . . . . . . . . . . . . . . 34 1.4.1.2.4 R/W--Read/Write . . . . . . . . . . . . . . . . . . . . 36 1.4.1.2.5 DBE--Data Bus Enable. . . . . . . . . . . . . . . . . . 36 1.4.1.2.6 VMA--Valid Memory Address . . . . . . . . . . . . . . . 36 1.4.1.2.7 BA--Bus Available . . . . . . . . . . . . . . . . . . . 37 1.4.1.2.8 RDY--Ready. . . . . . . . . . . . . . . . . . . . . . . 37 1.4.1.2.9 NMI--Non-Maskable Interrupt . . . . . . . . . . . . . . 38 1.4.1.2.10 IRQ--Interrupt Request . . . . . . . . . . . . . . . . 38 1.4.1.2.11 RES--Reset . . . . . . . . . . . . . . . . . . . . . . 40 1.4.2 The MCS6502 . . . . . . . . . . . . . . . . . . . . . . . . 41 1.4.2.1 Product Characteristics . . . . . . . . . . . . . . . . . 41 1.4.2.2 Device Timing--Requirements and Generation. . . . . . . . 41 1.4.2.3 SYNC Signal . . . . . . . . . . . . . . . . . . . . . . . 44 1.4.2.4 S.O--Set Overflow . . . . . . . . . . . . . . . . . . . . 44 1.4.3 The MCS6503, MCS6504 and MCS6505. . . . . . . . . . . . . . 47 1.5 Peripheral Interface Device--MCS6520. . . . . . . . . . . . . 50 1.5.1 Introduction. . . . . . . . . . . . . . . . . . . . . . . . 50 1.5.2 Organization of the MCS6520 . . . . . . . . . . . . . . . . 51 1.5.2.1 Data Input Register . . . . . . . . . . . . . . . . . . . 54 1.5.2.2 Control Registers (CRA and CRB) . . . . . . . . . . . . . 54 1.5.2.3 Data Direction Registers (DDRA, DDRB) . . . . . . . . . . 55 1.5.2.4 Peripheral Output Registers (ORA, ORB). . . . . . . . . . 55 1.5.2.5 Interrupt Status Control. . . . . . . . . . . . . . . . . 55 1.5.2.6 Peripheral Interface Buffers (A, B) and Data Bus Buffers (DBB) . . . . . . . . . . . . . . . . . . . . 55 1.5.3 Interface Between MCS6520 and the MCS650X Family of Microprocessors. . . . . . . . . . . . . . . . . . . . 56 1.5.3.1 Data Bus (DO-D7). . . . . . . . . . . . . . . . . . . . . 56 1.5.3.2 Enable (E). . . . . . . . . . . . . . . . . . . . . . . . 56 1.5.3.3 Read/Write (R/W). . . . . . . . . . . . . . . . . . . . . 56 1.5.3.4 Chip-Select Lines (CSl, C52, C53) . . . . . . . . . . . . 56 1.5.3.5 Register-Select Lines (RS, RS1) . . . . . . . . . . . . . 58 1.5.3.5.1 Reading the Peripheral A I/O Port . . . . . . . . . . . 59 1.5.3.5.2 Reading the Peripheral B I/O Port . . . . . . . . . . . 59 1.5.3.6 Reset (RES) . . . . . . . . . . . . . . . . . . . . . . . 63 1.5.3.7 Interrupt Request Line (IRQA, IRQB) . . . . . . . . . . . 63 1.5.3.7.1 Control of IRQA . . . . . . . . . . . . . . . . . . . . 63 1.5.3.7.2 Control of IRQB . . . . . . . . . . . . . . . . . . . . 64 -vi- 1.5.4 Interface Between MCS6520 and Peripheral Devices. . . . . . 64 1.5.4.1 Peripheral I/O Ports. . . . . . . . . . . . . . . . . . . 64 1.5.4.1.1 Peripheral A I/O Port (PA0-PA7) . . . . . . . . . . . . 65 1.5.4.1.2 Peripheral B I/O Port (PB0-PB7) . . . . . . . . . . . . 65 1.5.4.2 Interrupt Input/Peripheral Control Lines (CA1, CA2, CB1, CB2). . . . . . . . . . . . . . . . . . . . . 66 1.5.4.2.1 Peripheral A Interrupt Input/Peripheral Control Lines (CB1, CB2). . . . . . . . . . . . . . . . 66 1.5.4.2.2 Peripheral B Interrupt Input/Peripheral Control Lines (CB1, CB2). . . . . . . . . . . . . . . . 67 1.5.5 Summary of MCS6520 Operation. . . . . . . . . . . . . . . . 67 1.5.5.1 Control Register Operation. . . . . . . . . . . . . . . . 67 1.5.5.2 MCS6520 Operation in MC6500 Systems . . . . . . . . . . . 70 1.6 Peripheral Interface/Memory Device--MCS6530 . . . . . . . . . 71 1.6.1 Introduction. . . . . . . . . . . . . . . . . . . . . . . . 71 1.6.2 Pinout Description. . . . . . . . . . . . . . . . . . . . . 71 1.6.2.1 Reset (RES) . . . . . . . . . . . . . . . . . . . . . . . 71 1.6.2.2 Input Clock . . . . . . . . . . . . . . . . . . . . . . . 73 1.6.2.3 Read/Write (R/W). . . . . . . . . . . . . . . . . . . . . 73 1.6.2.4 Interrupt Request (IRQ) . . . . . . . . . . . . . . . . . 73 1.6.2.5 Data Bus (D0-D7). . . . . . . . . . . . . . . . . . . . . 73 1.6.2.6 Peripheral Data Ports . . . . . . . . . . . . . . . . . . 73 1.6.2.7 Address Lines (A0-A9) . . . . . . . . . . . . . . . . . . 74 1.6.3 Internal Organization . . . . . . . . . . . . . . . . . . . 74 1.6.3.1 ROM--1K Byte (8K Bits). . . . . . . . . . . . . . . . . . 74 1.6.3.2 RAM--64 Bytes (512 Bits). . . . . . . . . . . . . . . . . 76 1.6.3.3 Internal Peripheral Registers . . . . . . . . . . . . . . 76 1.6.3.4 Interval Timer. . . . . . . . . . . . . . . . . . . . . . 76 1.6.4 Addressing. . . . . . . . . . . . . . . . . . . . . . . . . 78 1.6.4.1 One-Chip Addressing . . . . . . . . . . . . . . . . . . . 80 1.6.4.2 Seven-Chip Addressing . . . . . . . . . . . . . . . . . . 80 1.6.4.3 I/O Register--Timer Addressing. . . . . . . . . . . . . . 80 CHAPTER 2 CONFIGURING THE MICROCOMPUTER SYSTEM 2.1 The System Configuration Task . . . . . . . . . . . . . . . . 84 2.2 Input/Output Techniques . . . . . . . . . . . . . . . . . . . 85 2.2.1 The General Purpose Input/Output (I/O) Port . . . . . . . . 85 2.2.2 The Special Purpose Peripheral Interface Device . . . . . . 85 2.2.3 Configuring the General Purpose I/O Port. . . . . . . . . . 87 2.2.3.1 Assignment of Outputs . . . . . . . . . . . . . . . . . . 88 2.2.3.2 Assignment of Inputs. . . . . . . . . . . . . . . . . . . 88 2.2.4 Power-On Considerations . . . . . . . . . . . . . . . . . . 90 -vii- 2.2.5 Handshaking . . . . . . . . . . . . . . . . . . . . . . . . 94 2.2.5.1 Handshaking on Data Transfers from the Processor. . . . . 94 2.2.5.2 Handshaking on Data Transfers into the Processor. . . . . 95 2.3 Configuring the Interface Between the Microprocessor and the Support Chips . . . . . . . . . . . . . . . . . . . . 99 2.3.1 Assignment of Addresses in the MCS6500 System . . . . . . . 99 2.3.1.1 ROM Address Assignment. . . . . . . . . . . . . . . . . . 102 2.3.1.2 RAM Address Assignment. . . . . . . . . . . . . . . . . . 102 2.3.2 Additional Address Assignment Techniques. . . . . . . . . . 104 2.3.3 Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . 104 2.3.3.1 Interrupt Prioritizing. . . . . . . . . . . . . . . . . . 106 2.3.3.2 Example 1: Selecting the Interrupt Vector . . . . . . . . 106 2.3.3.3 Example 2: Using the Processor Software Power . . . . . . 108 2.3.4 The Application of ROY to Controlling the Mem- ory Interface . . . . . . . . . . . . . . . . . . . . . . . 108 2.3.4.1 Interface Slow PROMs. . . . . . . . . . . . . . . . . . . 108 2.3.4.2 Direct Memory Address (DMA) Techniques. . . . . . . . . . 112 2.3.4.3 Control of Dynamic RAMs in the MCS6500 System . . . . . . 113 2.3.5 Hold-Time Control--MCS65O1. . . . . . . . . . . . . . . . . 117 2.4 Additional System Considerations. . . . . . . . . . . . . . . 119 2.4.1 Peripheral Interface Devices. . . . . . . . . . . . . . . . 119 2.4.2 RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 2.4.3 ROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 2.5 Evaluating System Performance . . . . . . . . . . . . . . . . 121 CHAPTER 3 BRINGING UP THE MCS6500 3.0 Introduction to Microcomputer Testing . . . . . . . . . . . . 123 3.1 Static Testing. . . . . . . . . . . . . . . . . . . . . . . . 124 3.1.1 Introduction. . . . . . . . . . . . . . . . . . . . . . . . 124 3.1.2 Single Cycle Execution. . . . . . . . . . . . . . . . . . . 124 3.1.3 Single Instruction Execution. . . . . . . . . . . . . . . . 127 3.2 Dynamic Testing . . . . . . . . . . . . . . . . . . . . . . . 130 3.2.1 Introduction. . . . . . . . . . . . . . . . . . . . . . . . 130 3.2.2 Externally Induced Loops. . . . . . . . . . . . . . . . . . 130 3.2.3 Software Loops. . . . . . . . . . . . . . . . . . . . . . . 132 -viii- 3.3 System Diagnosis Using Hardware Programmer Aids . . . . . . . 133 3.3.1 KIM Keyboard Input Monitor. . . . . . . . . . . . . . . . . 135 3.3.2 TIM--Teletype Input Monitor . . . . . . . . . . . . . . . . 136 3.3.3 MDT--Microcomputer Development Terminal . . . . . . . . . . 138 3.4 Microprocessor Start-Up Procedure . . . . . . . . . . . . . . 139 3.4.1 Introduction. . . . . . . . . . . . . . . . . . . . . . . . 139 3.4.2 System Power--Step 1. . . . . . . . . . . . . . . . . . . . 139 3.4.3 Basic System Timing--Step 2 . . . . . . . . . . . . . . . . 140 3.4.4 System Reset--Step 3. . . . . . . . . . . . . . . . . . . . 140 3.4.4.1 Static Analysis of System Details . . . . . . . . . . . . 144 3.4.4.2 Dynamic Analysis of System Details. . . . . . . . . . . . 145 3.4.4.2.1 Address Bus Verification. . . . . . . . . . . . . . . . 145 3.4.4.2.2 Data Bus Verification . . . . . . . . . . . . . . . . . 146 3.4.5 Detailed Component Cbeck. . . . . . . . . . . . . . . . . . 148 APPENDIX A . . . . . . . . . . . . . . . . . . . . . . . . . . . A-1 -ix- LIST OF FIGURES CHAPTER 1 THE MCS6500 MICROCOMPUTER SYSTEM 1.1 Organization of Microcomputer System . . . . . . . . . . . . . 5 1.2 Address Bus and Relation to Memory Field . . . . . . . . . . . 7 1.3 Portion of Read Only Memory Matrix . . . . . . . . . . . . . . 9 1.4 Pinout Comparison: MOS Technology MCS6501, Motorola MC6800 . . 13 1.5 Clock and Read/Write Timing Table (1 MHz Operation). . . . . . 17 1.6 Two-Phase Clock Timing . . . . . . . . . . . . . . . . . . . . 18 1.7 Timing for Reading Data from Memory of Peripherals . . . . . . 18 1.8 Timing for Writing Data to Memory or Peripherals . . . . . . . 19 1.9 Interrupt Wire OR'd Hardware Configuration from Peripheral Interface Devices to Microprocessor . . . . . . . . . . . . 24 1.10 Sequence to Service IRQ . . . . . . . . . . . . . . . . . . . 26 1.11 MCS650X Internal Architecture . . . . . . . . . . . . . . . . 29 1.12 MCS6501 Pinout Designations . . . . . . . . . . . . . . . . . 33 1.13 MCS650X System Timing Diagram . . . . . . . . . . . . . . . . 35 1.14 Examples of Interrupt Recognition by MCS650X. . . . . . . . . 39 1.15 MCS6502 Pinout Designation. . . . . . . . . . . . . . . . . . 42 1.16 MCS6502 Time Base Generation--Crystal Controlled. . . . . . . 43 l.16a MCS6502 Parallel Mode Crystal Controlled Oscillator . . . . . 43 l.16b MCS6502 Series Node Crystal Controlled Oscillator . . . . . . 43 1.17 MCS6502 Time Base Generator--RC Network . . . . . . . . . . . 43 1.18 MCS6502 SYNC Signal . . . . . . . . . . . . . . . . . . . . . 45 1.19 Functional Features of MCS6503, MCS6504, MCS6505. . . . . . . 46 1.20 MCS6503, MCS6504, MCS6505 Pinout Designations . . . . . . . . 48 1.21 MCS6503, MCS6504, MCS6505 Time Base Generation Crystal Controlled. . . . . . . . . . . . . . . . . . . . . . . . . . 49 1.22 MCS6503, MCS6504, MCS6505 Time Ease Generation RC Network . . 49 1.23 Basic MCS6520 Interface Diagram . . . . . . . . . . . . . . . 50 1.24 MCS6520 Pinout Designations Peripheral Interface Adaptor. . . 52 1.25 MCS6520 Internal Architecture . . . . . . . . . . . . . . . . 53 l.26a Microprocessor Interface Timing--Read. . . . . . . . . . . . 57 l.26b Microprocessor Interface Timing--Write . . . . . . . . . . . 57 l.27a Peripheral A Interface Timing. . . . . . . . . . . . . . . . 60 l.27b Peripheral B Interface Timing. . . . . . . . . . . . . . . . 61 l.28a Peripheral I/O Port A Buffer . . . . . . . . . . . . . . . . 62 1.28b Peripheral I/O Port B Buffer . . . . . . . . . . . . . . . . 62 1.29 Control Register Bit Designations . . . . . . . . . . . . . . 67 -x- 1.30 Control of Interrupt Inputs CAl, CBl. . . . . . . . . . . . . 68 l.31a Control of CA2 (CB2) as Interrupt Inputs (Bit 5 = "0") . . . 68 l.31b Control of CA2 Output Modes. . . . . . . . . . . . . . . . . 69 l.31c Control of CB2 Output Modes. . . . . . . . . . . . . . . . . 69 1.32 MCS6530 Pinout Designation. . . . . . . . . . . . . . . . . . 72 1.33 MCS6530 Internal Architecture . . . . . . . . . . . . . . . . 75 1.34 Basic Elements of Interval Timer. . . . . . . . . . . . . . . 77 1.35 Example of Interrupt Generated by Interval Timer. . . . . . . 79 1.36 MCS6530 One-Chip Address Encoding Diagram . . . . . . . . . . 81 1.37 MCS6530 Seven-Chip Addressing Scheme. . . . . . . . . . . . . 82 1.38 Addressing Decode for I/O Register and Timer. . . . . . . . . 83 CHAPTER 2 CONFIGURING THE MICROCOMPUTER SYSTEM 2.1 Control of Low Order Bit of MCS6520 Output Register. . . . . . 89 2.2 MCS6520 Control of Transistor Driven Solenoids . . . . . . . . 91 2.3a MCS6520 Control of PNP Transistor Driving Solenoid Coil . . . 93 2.3b MCS6520 Controlling Both Power and Drivers of Solenoid Cell . 93 2.4 MCS6520 Driving TTL Buffers. . . . . . . . . . . . . . . . . . 93 2.5 MCS6520 Controlling Solenoids with Enable Signal and TTL Interface . . . . . . . . . . . . . . . . . . . . . . . . . . 94 2.6 Write Handshake Sequence . . . . . . . . . . . . . . . . . . . 97 2.7 Read Handshake Sequence. . . . . . . . . . . . . . . . . . . . 98 2.8 Organization of Microcomputer System . . . . . . . . . . . . 100 2.9 Example of "AND" Function Using High Order Address Lines . . 101 2.10 Typical Address Assignments . . . . . . . . . . . . . . . . 103 2.11 Page Zero Chip-Select Addressing Scheme . . . . . . . . . . 105 2.12 Selecting the Interrupt Vector. . . . . . . . . . . . . . . 107 2.13 Using MCS6520 for Jump Indirect Interrupt Routines. . . . . 109 2.14a Priority Encoder Connected to Low Order Bits of MCS6520. . 110 2.14b Priority Encoder to Peripheral Interface Scheme. . . . . . 111 2.15 Software Program to Implement Interrupt from above Hardware Configuration . . . . . . . . . . . . . . . . . . . . . . . 111 2.16 Interfacing Scheme for Slow PROMs . . . . . . . . . . . . . 114 2.17 Logic Used to Generate Bus Available Signal for DMA Applications. . . . . . . . . . . . . . . . . . . . . . . . 114 2.18 Control Logic for Refresh Signal for Dynamic RAMs . . . . . 116 2.19 Timing Analysis of Data Hold Time . . . . . . . . . . . . . 118 -xi- CHAPTER 3 BRINGING UP THE MCS6500 3.1 Suggested Static Test Control Logic. . . . . . . . . . . . . 125 3.2 Single Cycle Timing. . . . . . . . . . . . . . . . . . . . . 126 3.3 Microprocessor Single Cycle Data Trap. . . . . . . . . . . . 128 3.4 Single Instruction Execution . . . . . . . . . . . . . . . . 129 3.5 Suggested Configuration for Dynamic Reset Testing. . . . . . 131 3.6 MCS6501 Clock Timing Signals . . . . . . . . . . . . . . . . 141 3.6a Improper Clocks . . . . . . . . . . . . . . . . . . . . . . 141 3.6b Proper Clocks . . . . . . . . . . . . . . . . . . . . . . . 141 3.7 Address Lines in MCS650X Systems . . . . . . . . . . . . . . 142 3.7a Proper Address Lines. . . . . . . . . . . . . . . . . . . . 142 3.7b Excess Address Line Loading . . . . . . . . . . . . . . . . 142 3.8 The Data Bus in MCS650X Systems. . . . . . . . . . . . . . . 143 -xii- CHAPTER 1 THE MCS6500 MICROCOMPUTER SYSTEM The past several years have seen the development of an exciting new concept in electrical design. Conventional system design is rapidly being revolution- ized by the large-scale, single-chip programmable microprocessor. The micro- computer started out as a relatively simple, difficult-to-use programmable device capable of handling simple control or computational problems. However, it has since matured into a powerful, inexpensive, easy-to-use device capable of controlling all but the most complex of systems. Three primary attributes of microprocessor-based systems are bringing about this revolution. They are: 1. Microprocessors allow a significant reduction in overall systems cost for products currently in production. Re-designing their products around the microprocessor is permitting many manufacturers to develop or maintain a price advantage over competitors. 2. The reduction in cost of microcomputer systems is opening up vast new markets for microprocessors. A great number of systems which were simply impossible or were at best impractical, are being designed and marketed today using the modern, low-cost microprocessors. 3. At the same time the price of microprocessors is dropping, the cap- ability is rapidly expanding. This also allows them to be designed into more systems than ever before. Anyone contemplating a new design or trying to reduce cost in an existing design must ask himself if a microprocessor will solve his problem. The success of the microprocessor is based on the fact that it allows the design engineer and programmer to apply their expertise in solving a multitude of design problems using cost effective ICs. A small number of large inte- grated circuits can be configured to solve design problems from the simplest to the most complex. -1- If the same integrated circuits are used to solve a multitude of unique designs, the first question one must ask is, "What makes them unique?" The answer is: Programming. Although many different designs may share common hard- ware, each has its own unique program. This brings us to another very important characteristic of microcomputers. The integrated circuit which makes each sys- tem unique is the "Read-Only Memory" (ROM) which stores the system program. It is relatively easy for the integrated circuit manufacturer to establish the particular pattern which uniquely defines the data in a ROM. As a result, the typical charge for "designing" a ROM is generally less than 10% of the cost of designing a totally custom logic chip. Further, the user benefits from high volume standard product which is still unique for his own application due to the "customization" of one element of his system. -2- 1.0 DESIGNING WITH MICROCOMPUTER SYSTEMS It will probably surprise many designers who are approaching the subject of microcomputer design for the first time when they discover that designing a system around a microprocessor is much the same as designing around conventional logic. The total approach is the same; the process differs only in the imple- mentation of each step. A brief examination of the system design process will help to put micro- computer design in perspective and will also assist in clarifying the purpose of this manual. One can expect to perform the following steps in designing a system: 1. Define the requirements of the system. What functions should it perform? 2. Define basic system components. 3. Complete design details. 4. Build and test prototypes. 5. Finalize design and begin production. Step 1 is true for any system and, in general, for any product. Step 2 is the first point of departure for microprocessor based designs. It is at this time that the designer must consider the possibility of using a microprocessor in his system. For the very cost-sensitive application he must look very care- fully at total systems cost. Can a microprocessor do the job within the price constraints imposed? At the other end of the design spectrum, the system de- signer must evaluate the capability of microprocessors to assure himself that the available devices can in fact perform the required function. Will a micro- processor be fast enough to run the system? Will it take more than one proces- sor? The purpose of this manual is to teach the designer how to effectively con- figure a microprocessor-based system and to evaluate the performance of the sys- tem. After this step, the design will be completed by development of the system program. Implementation of the system program is discussed in the Programming Manual. -3- 1.1 INTRODUCTION TO MICROCOMPUTER SYSTEMS 1.1.1 Organization of a Microcomputer System Figure 1.1 illustrates the basic organization of a microcomputer system. It is important that the designer understand the operation of each component as well as the operation of each data path in the system. Each of these is discussed separately below. In addition, the following discus- sion describes the operation of the overall system and the use of the vari- ous signal paths. 1.1.2 Basic Operation The microcomputer is a system which can be characterized as very simple in its detail and very complex in its overall operation. It carries out rather complex tasks by performing a large number of simple operations. Control of the system is primarily the responsibility of the processor. By putting out addresses to program memory, it controls the sequence of operations performed and by interpreting and executing the instructions which it receives from the program memory, it controls the actual operations carried out by the system. The processor is by far the most complex device in the system. For this reason, it is important to overall system cost that this part stay the same for many different appli- cations. In this way, the relatively high development cost can be shared by thousands of users. In addition, those thousands of users can all bene- fit from the economics of large-scale production. The processor causes the system to perform the desired operations by reading the first instruction in the program, and performing the very simple task dictated by the specific pattern of bits in this instruction (referred to as "executing" that instruction). It then goes on to the next instruc- tion in the program and executes it. This simple operation of fetching an instruction and executing it is performed over and over, each time on the next instruction in sequence. In this way the program instructs the pro- cessor to bring about the desired system operation. 1.1.3 Addressing Terms and Concepts Before entering into a detailed discussion of the system operation, it would be useful to define a few terms and to introduce a few concepts concerning addressing. This should assist in an understanding of the detailed discussions which follow. -4- Organization of Microcomputer System FIGURE 1.1 -5- 1.1.3.1 Bit The term "Bit" is a general term referring to anything that can be assigned to binary value, i.e., anything that can be given a value of 0 or 1. Thus, an eight-bit data bus is a set of 8 lines which can be assigned a value of logic 0 or logic 1. On these lines, the logic values are repre- sented by two different voltages or currents. Similarly, a 16-bit binary display can be built with 16 individual lamps. The logic 1 is represented by the lamp being on. In this text, reference is made to an 8-bit data bus, a 16-bit address bus, 4 bits of data, 8-bit registers, etc. In all cases, defini- tion of a bit remains the same. 1.1.3.2 Address Space The concept of an address space is very useful in understanding microcomputer systems. The term "address space" refers to the total set of addresses which the microprocessor can generate. For example, if a pro- cessor had only 4 address lines, it could generate the addresses 0 - 15 (binary 0000 to binary 1111). This would not be adequate for any microcom- puter operation and, consequently, the typical processor has between 12 and 16 address lines. Since each line can assume a value of 0 or 1, these de- vices can usually address from 4,096 to 65,536 separate addresses. Figure 1.2 contains a pictorial representation of the address space available in a typical 8-bit microcomputer with sixteen address lines. In addition to the general address space, this figure introduces the PAGE concept dis- cussed below. 1.1.3.3 The Address Page The concept of a PAGE in memory is very important in 8-bit micro- computer systems. The internal organization of an 8-bit processor is around 8-bit registers, 8-bit parallel data paths, etc. Most arithmetic operations, logic operations, etc. take place on 8 bits of data at a time. Likewise, the 16-bit counter which determines which instruction is being executed is actually divided into two 8-bit busses. One contains bits 0 - 7 (low order address bits) and the other contains bits 8 to 15 (high order address bits). With this in mind, one can think of the address space shown in Figure 1.2 as consisting of 256 blocks, each consisting of 256 specific address locations. Each of these blocks is referred to as a "PAGE" -6- -7- of memory. The high order 8 bits of the address (ADH) therefore indicates in which page the address is located, and the low order 8 bits (ADL) indi- cates a specific address on that page. The first page in memory (ADH = 00) is referred to as page zero. The next higher order page (ADH = 01) is referred to as page 1, etc. 1.1.4 System Components The block diagram in Figure 1.1 shows the basic components which comprise all microcomputer systems. Each of these blocks may consist of one or more integrated circuits and, in fact, the functions may be com- bined into single chips. However, the basic operation of each remains the same. 1.1.4.1 Clock Generator The clock generator produces a continuous waveform which is normally used to control all signal transitions within the system. It acts as the "heart" of the system. In the typical microcomputer system the address bus will change during one half of the clock cycle and the data will be transferred during the second half. In addition to interpreting the address, data and control lines, the processor and support chips must also examine the system clock to know when to put Out data or when to latch in data generated by another device. 1.1.4.2 Program Memory The program memory stores the sequence of instructions which com- prises the system program. Like any memory, this unit puts a pattern of 1's and 0's on the data bus in response to the address on the address bus input. Each unique address selects a set of 8 binary bits and places this data on the data bus. Note that it does not matter where the address is generated or where the data is used; the memory simply obeys the rule that, given an address, it will put the corresponding 8 bits of data on the data bus. A unique characteristic of most microprocessor-based systems is that the program is usually stored in "READ-ONLY" memories. The data is stored in a fixed pattern of bits in the memory. Figure 1.3 shows a sec- tion of a semiconductor READ-ONLY Memory (ROM). -8- Portion of Read Only Memory Matrix FIGURE 1.3 Since the data is stored in the physical configuration of the device, the data will not be lost when power is disconnected from the chip. In addi- tion, it is only necessary to insert the device into its socket to pro- vide the system program. The term "Read-Only Memory" refers to the fact that, in system operation, it is impossible for the processor to cause data to be stored in the device. The processor can only "READ" the data stored in the device during the manufacturing process. "READING" a memory in- volves the simple process of supplying an address to the device to obtain the corresponding 8 bits of data on the data bus. 1.1.4.3 Data Memory For temporary storage of input data, the results of arithmetic operations, etc., the microcomputer uses a Read/Write Memory, commonly re- ferred to as a RAM (Random Access Memory). The processor can store data in the RAM (called "WRITING" the RAM), or it can read back the data it has stored. As in the ROM, each address corresponds to eight memory cells. However, in a RAM the data must be placed into the memory by the processor and is stored in cross-coupled latches. Turning off the power to the chip will cause the loss of all data stored there. The data is said to be -9- "volatile." Data in a ROM is not lost when power is disconnected from the device; the data is therefore referred to as "non-volatile." "WRITING" data into a RAM takes place when the Write-Enable signal goes to the write state. At this time the data on the data bus will be stored into the eight memory cells corresponding to the address on the ad- dress bus. The processor can READ this same data by supplying the proper address and keeping the Write-Enable line in the Read state. 1.1.4.4 Input/Output Devices The Input/Output Devices are the circuits which interface the printer, keyboard, displays, etc. to the processor. These allow the pro- cessor to read data from the keyboard, to test the state of sensors and switches, and to display or to print the results of internal operations. No matter where data is generated, it must be in the form of 1's and 0's before the processor can work with it. Likewise, actions to be initiated by the processor must be triggered by 1's and 0's transferred by the processor to a set of output lines. The transfer of data from the processor to an output device is usually accomplished by "WRITING" the data out in much the same manner as the processor writes data into RAM. Each set of 8 input or output lines (referred to as "PORT") is given an address and the processor simply writes data to that address. For each "1" written out to the peripheral port an output is set high and for each "0," the corresponding output is set low. Although the basic concept of peripheral control is simple, the actual implementation of these interfaces can involve many sophisticated techniques designed to allow the processor to maximize its ability to con- trol peripherals and perform internal operations concurrently. These tech- niques are discussed in detail in Chapter 2 of this manual. 1.1.4.5 The Microprocessor At first glance it may seem strange to discuss the support chips in the microprocessor-based system before mentioning the processor. How- ever, this approach is necessitated by the fact that most of the inputs and outputs on the processor are aimed at properly controlling the support chips and peripheral devices discussed above. The address bus, the bi-directional data bus and the Write-Enable line allow the processor to exercise direct control over the rest of the system. The address bus puts out addresses to control the source or destination of data transfers. These addresses are derived from various -10- sources within the processor. During the fetch of instructions from pro- gram memory, the addresses are usually derived from a counter which con- trols execution of sequential instructions. Addresses for data transfers between the processor and RAM are usually derived directly from the program or are calculated from the data in the program and data in internal regis- ters. The bi-directional data bus serves as a path for transferring data into and out of the processors. The direction of the data transfer is de- termined by the Write-Enable line. Another special function found in modern microcomputer systems is the interrupt. This function allows the peripheral devices to directly affect the operation of the processor. When the interrupt signal is gener- ated, the processor usually completes its current instruction and then, under program control, will respond to the interrupt. The importance of this function is that it allows the processor to execute the system program without requiring the system program to monitor the status of the peripheral device. The software which handles the operation of each peripheral will be executed only when required. -11- 1.2 INTRODUCTION TO THE MCS65OX MICROPROCESSOR FAMILY The initial MOS Technology, Inc. microprocessor offering consists of the MCS6501, which is MC6800 compatible; the MCS6502, which has clock drivers on- chip; and three 28-pin processors, the MCS6503, MCS6504, and MCS6505. All of these devices are aimed at a specific range of applications. Therefore, it is important to develop an understanding of the capabilities of each and the dif- ferences between them. The MCS6501 has application in existing M6800 systems where conversion to the MOS Technology, Inc. processor is to be performed. This processor requires the full high-level two-phase clocks of the N6800 system. The MCS6502 is ex- pected to find application in all new designs which require a full 16-bit ad- dress bus. However, in the small cost-sensitive system, the 28-pin processors can represent a savings in both processor cost and printed circuit board area. The MCS6503, MCS6504, and MCS6505 will find application in all new designs where the system will operate within the addressing limits. 1.2.1 The MCS6501 The MCS6501 is the first member of the microprocessor family to be introduced. It is designed to be pin compatible with the M6800 and there- fore conversion from the MC6800 to the MOS Technology, Inc. MCS6501 re- quires only that the system be reprogrammed. This allows the M6800 user to take full advantage of the software power (addressing modes, etc.) of the MCS650X processor family. Although the conversion process is fairly simple, it is important to keep in mind the differences between the MC6800 and the MCS6501. The pins on the MCS6501 all do the same general function as those on the MC6800 but the function performed may differ somewhat in detail. Figure 1.4 contains a detailed, pin-for-pin comparison of these two processors. A thorough understanding of this table, along with an understanding of the MCS650X software will allow the system designer to perform the conversion with very little difficulty. The MCS6501 provides a full 16-bit address bus, 8-bit data bus and two interrupts. -12- | MOTOROLA MOS TECHNOLOGY | MOTOROLA MOS TECHNOLOGY PIN # 6800 6501 | PIN # 6800 6501 | | 1 Vss Vss | 21 Vss Vss 2* Halt Ready | 22 A12 A12 3 Ø1 (in) Ø1 (in) | 23 A13 A13 4 IRQ- IRQ- | 24 A14 A14 5* VMA VMA | 25 A15 A15 6 NMI- NMI- | 26 D7 D7 7 BA BA | 27 D6 D6 8 Vdd Vdd | 28 D5 D5 9* A0 A0 | 29 D4 D4 10 A1 A1 | 30 D3 D3 11 A2 A2 | 31 D2 D2 12 A3 A3 | 32 D1 D1 13 A4 A4 | 33 D0 D0 14 A5 A5 | 34 R/W R/W 15 A6 A6 | 35 N.C. N.C. 16 A7 A7 | 36 DBE DBE 17 A8 A8 | 37 Ø2 (in) Ø2 (in) 18 A9 A9 | 38* N.C. N.C. 19 A10 A10 | 39* TSC 20 A11 All | 40 Reset Reset | * DIFFERENCES PIN # MOTOROLA 6800 MOS TECHNOLOGY 6501 2 Halt - Stops processor after Ready - Stops Processor during completing current instruction. current instruction. Address Address Bus in off state. Bus reflects current address being read. 5 VMA - Signal determines when VMA - No need for Valid Memory address from processor is Address Signal. All addresses Valid. are valid at all times. This pin is internally tied to Vdd and can be used as a VMA signal in high state. 9 Address Bus uses Tri-State Address Bus uses TTL level Output Buffers. Output Drivers. 38 No Connection 39 T.S.C. - Three-State Control N.C. - No need for TSC since Controls all Three-State Address is not Three-State and Buffers, Address Bus and DBE Controls Three-State of Data Bus. Data Bus. Pinout Comparison MOS TECHNOLOGY INC. MCS65O1, MOTOROLA MC6800 FIGURE 1.4 -13- 1.2.2 The MCS6502 The second member of the processor family is a 40-pin device which provides all the features of the MCS6501, along with an "on-the-chip" oscil- lator and clock drivers. This device should be used in all new designs which require the capability of the 40-pin processors. The clock drivers can be driven with a single TTL level square wave or with the internal oscillator. The frequency of operation of the internal oscillator can be set by attaching an R-C combination to the chip and, if the clock stability is required, by attaching a crystal between the oscillator and ground. This feature totally eliminates the problems encountered in generating MC6800 type clock signals. As in the MCS6501, the MCS6502 provides a full 16-bit address bus, 8-bit bi-directional data bus and two interrupts. In addition, the MCS6502 provides a sync signal which indicates those cycles in which the processor is fetching an operation code from program memory. 1.2.3 The MCS6503, MCS6504 and MCS6505 Three 28-pin versions of the processor are available. These three differ in the number of address lines and the number of interrupts provided. Having all three options available allows the designer to tailor his pro- cessor to his particular application. The MCS6504 provides a total of 13 address pins and can, therefore, address a full 8K bytes in its memory space. However, this part provides only one interrupt request input, IRQ. The non-maskable interrupt (NMI) is not included in the pinouts of this device. The MCS6503 and MCS6505 provide one less address line. In the MCS6503, this address line is replaced with a second interrupt input, NMI. In the MCS6505, this address line is replaced by the RDY signal. A1l other functions on these processors are the same. The details of each of these pins are discussed in the following sections. The operation of the various busses, control signals, etc. is ex- actly the same on all MCS650X products with all processors obeying the sys- tem specifications discussed in Section 1.3 of this manual. -14- 1.3 MCS6500 SYSTEM CONCEPTS 1.3.1 Bus Structure The MCS6500 microcomputer system is organized around two primary busses. Each bus consists of a set of parallel paths which can be used to transfer binary information between the devices in a system. The first bus, known as the ADDRESS BUS, is used to transfer the address generated by the processor to the address inputs of the memory and peripheral interface devices. The processor is the only source of addresses in a normal system, so this bus is referred to as "unidirectional." The address bus consists of 16 lines on the MCS6501 and MCS6502. This allows the processor to access (READ or WRITE) up to a total of 65,536 memory words, registers, etc. In the MCS6503, MCS6504, and MCS65O5, the address bus contains fewer lines; therefore, they operate with a smaller "address space." This is discussed in detail in Section 1.1.3. The data bus in the MCS6500 microcomputer system consists of an 8-bit bi-directional data path. These lines transfer data from the processor to the selected memory word, etc. during a WRITE operation and from memory into the processor during a READ operation. All data and all instructions are transmitted on the data bus. The direction of the data transfers is controlled by the READ/WRITE (R/W) line on the processor. This line performs the Write Enable function described in Section 1.1.4.3. As long as the R/W line is high (> 2.4v DC), all data transfers will take place from memory to the processor (READ opera- tion). This line will go low only when the processor is going to WRITE data out to memory. As in most microcomputer systems, the timing of all data transfers is controlled by the system clock. The clock itself is actually two non- overlapping square waves. This two-phase clock system can best be thought of as two alternating positive-going pulses. This text will refer to the clocks as Phase One and Phase Two. A Phase One clock pulse is the positive pulse during which the address lines change and a Phase Two clock pulse is the positive pulse during which the data is transferred. The timing of the signals on the Address Bus, Data Bus, and R/W line are shown in Figures 1.5 through 1.8. All signal transitions are specified with respect to the Phase One and Phase Two clock signals. -15- In particular, the address lines and the R/W line will stabilize during Phase One, and all data transfers will take place during Phase Two. The specific timing specifications for operating at a 1 MHz clock rate are also given in Figure 1.5. Note that the sequence of operations will be the same for all processors. However, these timing specifications will change for devices which are specified to operate faster than 1.0 MHz. The address is guaranteed to be stable 300 nanoseconds after the leading edge of Phase One, and the data must be stable 100 nanoseconds before the trailing edge of Phase Two. At 1.0 MHz operation, this allows the memory devices approximately 575 ns to make data available on the data bus. Al- though there are many factors which determine the actual data and address generated within the system, it is important to keep in mind that the basic operation shown in Figures 1.6, 1.7 and 1.8 does not change. These figures specify the system bus discipline which applies to all MOS Technol- ogy, Inc. processors and support chips. 1.3.2 Processor Interrupts Through the generation of processor interrupt signals, the peri- pheral devices (printers, keyboards, etc.) can request service from the processor. Although this technique is relatively simple in concept, the proper generation and control of interrupts is one of the most important problems which the designer will face. Total system capability can be greatly expanded if the processor is required to execute the peripheral software only when it is absolutely necessary. This is the goal of a well- planned interrupt structure. The interrupt structure is very much a sys- tems sophistication problem since it is the entire system which must pro- perly respond to the interrupt inputs. In fact, the actual signals to which the system must respond are usually applied to the inputs of a peri- pheral interface device. In this device, the interrupts are enabled, dis- abled and latched until the interrupt is processed. The peripheral inter- face device generates signals which meet the requirements of the processor interrupt inputs. There are two interrupt input lines to the microprocessor, IRQ (Interrupt Request) and NMI (Non-Maskable Interrupt). Since the requirements of the two interrupt inputs differ, they will be discussed separately below. The response of the processor to these in- puts is very similar, however, after the interrupt is recognized. For this -16- Clock and Read/Write Timing Table (1MHz Operation) FIGURE 1.5 -17- Two Phase Clock Timing FIGURE 1.6 Timing for Reading Data from Memory or Peripherals FIGURE 1.7 -18- Timing for Writing Data to Memory or Peripherals FIGURE 1.8 -19- reason, the internal operation of the processor during interrupt servicing is discussed in the detailed analysis of the processor chip. Instead, this section will concentrate on the system level considerations which are re- quired to assure proper operation of the interrupt structure. 1.3.2.1 Applications for Interrupts One of the most important tasks facing the microcomputer system designer is the determination of those signals which will cause processor interrupts and those operations which will take place in response to these interrupts. A detailed discussion of these considerations is included in Chapter 2 of the manual; however, a few examples of interrupt-driven opera- tions will be presented here to help the designer develop an understanding for why this technique is used extensively in microcomputer systems. Example 1--A Fully-Decoded Keyboard The problem of data entry is solved in many systems by a key- board. In small systems, the interpretation of the binary code associated with each key can be determined by the processor. However, in large data terminals, the keyboard usually includes an encoder which generates the unique code corresponding to each key. When a key is closed, the corre- sponding code is placed on the output pins and a strobe signal is generated to indicate that a key has been pressed. The keyboard represents a perfect candidate for interrupt- driven operation. The interrupts occur relatively infrequently and the operation to be performed is relatively simple. The keyboard strobe line is connected directly to an interrupt input on a peripheral interface de- vice. Each time a strobe signal is generated, an interrupt occurs, the processor reads the data on the peripheral port into memory, analyzes this data and then returns to the program that was in process. If no keys are pressed, the processor spends no time at all in servicing the keyboard. Without the interrupts, the processor would have to read the keyboard data into memory periodically in order to detect an active key. This operation would be performed about every fifty to one hundred milli- seconds. In addition to detecting an active key, the processor must make sure that each separate activation of a key is detected once and only once. This is discussed in Sections 1.3.2.5 and 1.3.2.6. This software is much more complex than the simple interrupt routine. Another drawback of non- interrupt processing is that the processor is required to spend a periodic -20- portion of its time on the keyboard. In many systems, this is not a prob- lem, but in large terminals, etc., the time spent checking for keyboard strobes could be better spent in other operations. The designer must, therefore, ask himself if the system under development is such that the processor can perform the keyboard strobe checking function while still completing its other tasks. Example 2--A Scanned Display Although time is a major factor in determining the necessity of interrupts, the interrupt technique can also be extremely useful when per- forming parallel operations. A prime example of this can be found in a system which contains a digital display and/or printer. A digital display is usually "scanned" such that each digit is driven for a short period of time in sequence. The entire display is scanned at a rate which the eye cannot detect. However, it can be noted here that the display requires scan-related attention from the processor at fixed intervals. It is very difficult for the processor to calculate repetitive time intervals while it is performing its normal system program routines. The processor would much prefer to run the system program with- out consideration for the display time intervals, only executing the display software when it is required. A solution to the above problem is the generation of processor interrupts at fixed intervals using an external counter or clock. Each time an interrupt occurs, the data for the next digit in the display is placed on an output port. The processor then returns to the program it had been executing. Both of the operations described above represent solutions to system problems. Events which happen very infrequently and events which must be performed in parallel with other events or in parallel with the main system program should be seriously considered as candidates for inter- rupts. Additional considerations are described in Chapter 2 of this manual; however, it is important to note here that the typical system may have several sources of interrupts, each with its own timing and each with its own set of operations which must be performed in response to the interrupts. -21- 1.3.2.2 Interrupt Prioritizing After a careful analysis of the total system and a determination of all the sources of interrupts, the designer must ask himself, "What hap- pens if more than one interrupt source requires attention at one time?" A priority level must be established between the various interrupt sources. Which ones must be taken care of within a very short period? Which ones can be put off for a while? This prioritizing and the technique for select- ing among several concurrent interrupts is very important to the system operation and should be established early in the system development process. The MCS650X-based system can employ several hardware methods of determining the highest priority active interrupt. These usually involve using a special "priority encoder" which allows the processor to go di- rectly to the software which services the highest priority interrupt. After this is complete, it will go to the next higher priority and execute that software. However, the MCS650X family provides a much less expensive method of interrupt prioritizing. This is the "polled" interrupt. With this technique, each time an active interrupt source is detected, the pro- cessor executes a "polled" interrupt program that interrogates the highest priority interrupt, then the next highest and so on until an active inter- rupt is located. The program services that interrupt and returns to the "polled" interrupt program and continues to interrogate the next highest priority interrupt until all have been interrogated or clears the interrupt disable to allow nested interrupts. The "polled" interrupt program is al- ways executed when an interrupt occurs so that all interrupts that occur concurrently will be serviced in order of priority level. Several hardware techniques for prioritizing interrupts are dis- cussed in Chapter 2 of this manual. The next section, however, describes the system interconnect which allows use of the simple "polled" interrupt. 1.3.2.3 System Interconnect for Interrupts In the simple "polled" interrupt technique for prioritizing inter- rupts, the interrupt software actually determines the highest priority active interrupt. The IRQ or NMI interrupt request signals simply cause the processor to jump to the polling software. For this reason, it is possible to "OR" the various interrupt signals together to form the signal for the processor. Any active inter- rupt source will then cause the processor to do the interrupt polling and -22- servicing operation. Provision for generation of this OR function is pro- vided in the MCS6500 family peripheral interface devices. Since these peripheral adapters perform many of the enabling and latching functions necessary for proper interrupt servicing, the peripheral adaptor interrupt output then provides the actual signal which interrupts the processor. These interrupt outputs can be "WIRE-OR'd" by connecting them all together and then connecting this single line to the processor. This input should then be pulled to +5V with a resistor. Any one of the interrupt outputs on the peripheral adaptors can then pull this interrupt low. This simple configuration is shown in Figure 1.9. 1.3.2.4 Interrupt Servicing Although a great deal has been said previously about the process of establishing interrupts and determining just what happens in response to an interrupt, it would be useful to detail the sequence which takes place when an interrupt is recognized by the processor. This will establish a basis for understanding of the details of the processor interrupt inputs. An interrupt request is signaled by a GND (< 0.4v) signal on the interrupt request input. This interrupt will be recognized after the pro- cessor completes the instruction which it is currently executing. The next step is to store enough of the contents of the internal processor registers to assure that the processor can resume execution of the program which was interrupted. In particular, the Program Counter and the Processor Status Register are stored in a series of memory locations specified by another internal register, the Stack Pointer. As discussed in Chapter 9 of the Programming Manual, saving the contents of the Program Counter and Proces- sor Status register uniquely defines, in memory, the state of the micro- processor at the time the interrupt occurred. The processor then goes to two fixed locations in memory to determine the address low and address high of the interrupt software. The operation to this point is automatic and is determined by the internal processor logic. After the processor has properly set the address bus, execution of the interrupt program commences. Everything which occurs subsequently is determined by the system software. The total interrupt software described above will consist of a com- plex combination of polling and interrupt servicing routines. However, unless -23- Interrupt Wire OR'd Hardware Configuration from Peripheral Interface Devices to Microprocessor FIGURE 1.9 -24- a hardware prioritizing scheme is used, the actual system interconnections will not become any more complex than that shown in Figure 1.9. 1.3.2.5 Interrupt Request (IRQ) As stated in Section 1.3.2, the two interrupt lines for the micro- processor are IRQ and NMI. The requirements for proper operation of the maskable Interrupt Request input (IRQ) are more stringent than for the second interrupt input, NMI. This is due primarily to the fact that NMI is edge-sensitive. With the IRQ input, the processor will be interrupted any time the signal on IRQ is GND (< 0.4v) and the internal Interrupt Dis- able flag is cleared. The Interrupt Disable flag (I) is a single bit in the internal Processor Status Register. The details of this register are described in Section 3.2 of the Programming Manual. In the processing of interrupt request from the IRQ input, the I flag is extremely important. This is the element which assures that an interrupt will be recognized and serviced only once for each request and only when an interrupt is desired. This is described in detail below. Figure 1.10 details the sequence of operations which should take place during the servicing of an IRQ interrupt. A positive or negative transition of the signal from the peripheral device (printer, keyboard, etc.) is detected on the edge-sensitive inputs to the peripheral interface device. If the interrupt is enabled within the peripheral interface de- vice, the interrupt request output (IRQ) on this chip will go low. The interrupt condition is latched within the peripheral interface device to allow sufficient time for the processor to poll the interrupt sources, assuring that the interrupt signal will not be cleared before the polling can be completed. This latch is reset by the processor as it executes the software associated with that interrupt. Details of this operation are described in Section 1.4.1.2.10 The Interrupt Disable flag (I) is set automatically when the pro- cessor recognizes an interrupt. This assures that this same interrupt will not be recognized again. Resetting this flag can be performed manually with an instruction in the program or automatically with a "Return from Interrupt" instruction. It is very important that "I" not be cleared before the interrupt input is reset. Performing the "Clear I" instruction too early in the program can cause this same interrupt to be recognized again. -25- Sequence to Service IRQ FIGURE 1.10 -26- The processor will then proceed to service this as if it were a new inter- rupt. 1.3.2.6 Non-Maskable Interrupt (NMI) The NMI input to the processor is edge-sensitive. To cause an interrupt to occur, there must be a negative transition of the signal on the NMI input. This negative transition will cause a single interrupt to occur. After servicing the interrupt, the processor will ignore this input until the NMI signal goes high (> +2.4v) and then back to ground. The response to an NMI interrupt signal cannot be disabled within the processor. After the processor completes the instruction being exe- cuted, it will recognize the interrupt and will proceed to service the interrupt as described in the previous section. The proper discipline to employ in all interrupts is for the interrupt signal to be latched until the processor completes servicing the interrupt. This method of operation is assured if all the interrupts are connected to the interrupt inputs of the peripheral interface devices in the family. Processing of multiple interrupts in a polled interrupt structure requires that all of the interrupts be polled before executing a "Return from Interrupt" instruction. This is necessitated by the "WIRE-OR" tech- nique for combining the interrupts, since no knowledge exists of which line went to ground. If one of the interrupts is left unserviced, it will hold the NMI signal to ground, disabling the interrupts from all other sources since it is necessary for the NMI signal to go high (> 2.4v) and back low again for an interrupt to occur. This is not true for the IRQ input since this latch is level-sensitive. Performing a "Return from Interrupt" before all IRQ interrupt sources are serviced will simply cause another IRQ inter- rupt to occur. 1.3.3 System Reset One of the basic system control functions is the system RESET signal. Whether this signal is generated automatically by external power-on circuitry or manually from a push-button switch, the system components must obey a fixed set of rules to assure proper system operation. This is particularly true for the peripheral interface devices. -27- In the MCS650X-based systems, an assumption is made that RESET pins on all peripheral interface devices and on the processor will be held low during power-on until the supply voltages and the clocks have stabilized. This procedure assures that the peripheral pins will remain in a known state until the entire system is initialized and the processor is ready to assume control of the output lines, i.e., is ready to run the system pro- gram. It should be mentioned that in the entire set of microcomputer chips, the contents of latches, registers, etc. is totally random after power is applied. On the peripheral output pins, random data can be disastrous. The only way to force these lines to a known condition is to apply the RESET signal. The designer can then make sure that the known condition will not cause spurious operations in the peripheral devices. The effect of RESET on the peripheral chips is discussed in the analysis of each chip. In the processor, the single register which must be placed in a known state is the program counter. This is the register which se- lects the instructions to be executed. The RESET input causes the program counter to go to the first instruction in the system program. The specific details of this operation are discussed in Section 1.4.1.2.11. There is one other very important function performed by the RESET input on the peripheral interface devices. Although the recognition of the processor interrupt signals is automatic and does not depend on software, the sequence of operations performed by the processor to totally service an interrupt is determined by the program. Until the various internal regis- ters in the processor have been initialized, the processor is not ready to respond properly to any external interrupts. For this reason, it is im- portant that the system RESET disable all external interrupt signals until they are enabled by the processor. The programmer can then make sure that the system has been properly initialized before the interrupts are enabled. -28- NOTE: 1. CLOCK GENERATOR IS NOT INCLUDED ON MCS6501 2. ADDRESSING CAPABILITY AND CONTROL OPTIONS VARY WITH EACH OF THE MCS650X PRODUCTS. MCS650X Internal Architecture FIGURE 1.11 -29- 1.4 THE MICROPROCESSORS 1.4.1 The MCS6501 1.4.1.1 Introduction The members of the MCS650X microprocessor family contain very similar internal architectures. A block diagram of this architecture is shown in Figure 1.11. This section begins with an analysis of this block diagram, discussing the function of the various registers, data paths, etc. A detailed discussion of the operation of the various pins on the chip fol- lows. The internal organization of the processor can be split into two sections. In general, the instructions obtained from program memory are executed by implementing a series of data transfers in one section of the chip (register section). The control lines which actually cause the data transfers to take place are generated in the other section (control section). Instructions enter the processor on the data bus, are latched into the instruction register, and are then decoded along with timing sig- nals to generate the register control signals. The timing control unit keeps track of the specific cycle being executed. This unit is set to "T0" for each instruction fetch cycle and is advanced at the beginning of each Phase One clock pulse. Each instruc- tion starts in T0 and goes to T1, T2, T3, etc. for as many cycles as are required to complete execution of the instruction. Each data transfer, etc., which takes place in the register section is caused by decoding the contents of both the instruction register and the timing counter. Additional control lines which affect the execution of the instruc- tions are derived from the Interrupt logic and from the Processor Status register. The Interrupt logic controls the processor interface to the interrupt inputs to assure proper timing, enabling, sequencing, etc. which the processor recognizes and services. The Processor Status register contains a set of latches which serve to control certain aspects of the processor operation, to indicate the results of processor arithmetic and logic operations, and to indicate the status of data either generated by the processor or transferred into the processor from outside. Since the real work of the processor is carried on in the register section of the chip, a detailed study will be made of this section. The components are: -30- * Data Bus Buffers * Input Data Latch (DL) * Program Counter (PCL, PCH) * Accumulator (A) * Arithmetic Logic Unit (ALU) * Stack Pointer (S) * Index Registers (X, Y) * Address Bus Latches (ABL, ABH) * Processor Status Register (P) At 1 MHz, the data which comes into the processor from the program memory, the data memory, or from peripheral devices, appears on the data bus during the last 100 nanoseconds of Phase Two. No attempt is made to actually operate on the data during this short period. Instead, it is simply transferred into the input data latch for use during the next cycle. The data latch serves to trap the data on the data bus during each Phase Two pulse. It can then be transferred onto one of the internal busses and from there into one of the internal registers. For example, data being transferred from memory into the accumulator (A) will be placed on the in- ternal data bus and will then be transferred from the internal data bus into the accumulator. If an arithmetic or logic operation is to be per- formed using the data from memory and the contents of the accumulator, data in the input data latch will be transferred onto the internal data bus as before. From there it will be transferred into the ALU. At the same time the contents of the accumulator will be transferred onto a bus in the reg- ister section and from there into the second input to the ALU. The results of the arithmetic or logic operation will be transferred back to the accumu- lator on the next cycle by transferring first onto the bus and then into the accumulator. All of these data transfers take place during the Phase One clock pulse. The program counter (PCL, PCH) provides the addresses which step the processor through sequential instructions in the program. Each time the processor fetches an instruction from program memory, the contents of PCL is placed on the low order eight bits of the address bus and the con- tents of PCH is placed on the high order eight bits. This counter is incremented each time an instruction or data is fetched from program memory. -31- The accumulator is a general purpose 8-bit register which stores the results of most arithmetic and logic operations. In addition, the accu- mulator usually contains one of the two data words used in these operations. All logic and arithmetic operations take place in the ALU. This includes incrementing and decrementing of internal registers (except PCL and PCH). However, the ALU cannot store data for more than one cycle. If data is placed on the inputs to the ALU at the beginning of one cycle, the result is always gated into one of the storage registers or to external memory during the next cycle. Each bit of the ALU has two inputs. These inputs can be tied to various internal busses or to a logic zero; the ALU then generates the SUM, AND, OR, etc. function using the data on the two inputs. The stack pointer (S) and the two index registers (X and Y) each consist of 8 simple latches. These registers store data which is to be used in calculating addresses in data memory. The specific operation of each of these is discussed in detail in the Programming Manual. The address bus buffers (ABL, ABH) consist of a set of latches and TTL compatible drivers. These latches store the addresses which are used in accessing the peripheral devices (ROM, RAM, and I/O). 1.4.1.2 The MCS6501 Pinouts Figure 1.12 shows a diagram of the MCS6501 microprocessor with the various pins designated. These pins and their use in microcomputer systems are discussed separately below. 1.4.1.2.1 Vcc, Vss--Supply Lines The Vcc and Vss pins are the only power supply connections to the chip. The supply voltage on pin 8 is +5.0 V DC + 5%. The absolute limit on the Vcc input is +7.0 V DC. 1.4.1.2.2 AB00-AB15--Address Bus The address bus buffers on the MCS650X family of microprocessors are push/pull type drivers capable of driving at least 130 pf and 1 stan- dard TTL load. The address bus will always contain known data as detailed in Appendix A. The addressing technique involves putting an address on the address bus which is known to be either in program sequence, on the same -32- MCS6501 Pinout Designations FIGURE 1.12 -33- page in program memory or at a known point in RAM. A brief study of Appen- dix A will acquaint the designer with the detailed operation of this bus. The various processors differ somewhat in the number of address lines provided. In particular, the MCS6504 provides thirteen address lines (AB00 - AB12) and the MCS6503 and MCS6505 provide twelve (AB00 - AB11). As a result, the MCS6504 can address 8,192 bytes of memory and the MCS6503 and MCS6505 can address 4,096 bytes. This total address space should prove to be more than sufficient for the small, cost-sensitive systems where these devices should find their greatest application. The specific timing of the address bus is exactly the same for all the processors. The address is valid 300 ns (at 1 MHz clock rate) into the Ø1 clock pulse and stays stable until the next Ø1 pulse. This specifi- cation will only change for processors which are specified to operate at a higher clock rate. Figure 1.13 details the relation of address bus to other critical signals. Because of the reduced number of address lines on the 28-pin processors, it is possible to write a program which attempts to access non- existent memory address space, i.e., the address bits 13, 14, or 15 set to logic "1." These upper address bits in the program will be ignored and the program will drop into existing address space. This assumes proper memory management when using devices of large addressing capability such that the addressed memory space will fit within the constraints of a device with smaller available memory addressing capability. 1.4.1.2.3 DB0-DB7--Data Bus The processor data bus is exactly the same for the processors currently available and for the software-compatible processors which will be introduced in the near future. All instructions and data transfers be- tween the processor and memory take place on these lines. The buffers driv- ing the data bus lines have full "three-state" capability. This is neces- sitated by the fact that the lines are bi-directional. Each data bus pin is connected to an input and an output buffer, with the output buffer remaining in the "floating" condition except when the processor is transferring data into or out of one of the support chips. All inter-chip data transfers take place during the Phase Two clock pulse. During Phase One the entire data bus is "floating." -34- MCS650X System Timing Diagram FIGURE 1.13 -35- The data bus buffer is a push/pull driver capable of driving 130 pf and 1 standard TTL load at the rated speed. At a 1 MHz clock rate, the data on the data bus must be stable 100 ns before the end of Phase Two. This is true for transfers in either direction. Figure 1.13 details the relationship of the data bus to other signals 1.4.1.2.4 R/W--Read/Write The Read/Write line allows the processor to control the direc- tion of data transfers between the processor and the support chips. This line is high except when the processor is writing to memory or to a peri- pheral interface device. All transitions on this line occur during the Phase One clock pulse (concurrent with the address lines). This allows complete control of the data transition which takes place during the Phase Two clock pulse. The R/W buffer is similar to the address buffers. They are capable of driving 130 pf and one standard TTL load at the rated speed. Again, Figure 1.13 details the relative timing of the R/W line. 1.4.1.2.5 DBE--Data Bus Enable On the MCS6501, a data bus enable signal is provided to allow external enabling of the data bus. This line is connected directly to the Phase Two input clock signal for any normally operating system and is de- tailed in Figure 1.13. The DBE signal affects only the data bus buffers. It does not affect processor timing and has no effect on the address or the R/W lines. This input is provided primarily for use in systems which use non-family devices for either the memory or the peripheral interface func- tions. In particular, it allows the data bus to be enabled for a period longer than the Phase Two clock pulse for systems requiring greater proces- sor hold time on the data bus. This application is covered in greater de- tail in Chapter 2. 1.4.1.2.6 VMA--Valid Memory Address As mentioned above, the MCS650X family of microprocessors always puts known addresses on the address bus and, as a result, does not require a VMA signal. However, to remain pin-compatible with the MC6800, the VMA pin -36- is connected internally to the Vcc power supply. This assures operation in systems in which VMA is part of the chip-select function. This pin is not available on the 28-pin processors. 1.4.1.2.7 BA--Bus Available The bus available signal is provided on the MCS65O1 to signal to a DMA controller, etc. that the processor is stopped and that the data and address busses can be used for other than processor program execution. This operation is similar to that of the MC6800 bus available signal except that much less time is required to stop the MCS6501 since the MC6800 requires completion of the current instruction before stopping. If no write operation takes place during the cycle in which the RDY signal goes low, the BA will go high (> 2.4v) during Phase Two of the same cycle. In general, BA will go high during the first Phase Two pulse during which the R/W line is high. For the current processors, the maximum time is 3-1/2 cycles. 1.4.1.2.8 RDY--Ready The RDY input delays execution of any cycle during which the RDY line is pulled low. This line should change during the Phase One clock pulse. This change is then recognized during the next Phase Two pulse to enable or disable the execution of the current internal machine cycle. This execution normally occurs during the next Phase One clock; timing is shown in Figure 1.13. The primary purpose of the RDY line is to delay execution of a program fetch cycle until data is available from memory. This has direct application in prototype systems employing light-erasable PROMs or EPROMs. Both of these devices have relatively slow access times and require imple- mentation of the RDY function if the processor is to operate at full speed. Without the RDY function a reduction in the frequency of the system clock would be necessary. The RDY function will not stop the processor in a cycle in which a WRITE operation is being performed. If the ROY line goes from high to low during a WRITE cycle the processor will execute that cycle and will then stop in the next READ cycle (R/W = 1). -37- 1.4.1.2.9 NMI--Non-Maskable Interrupt The NMI input, when in the interrupted state, always interrupts the processor after it completes the instruction currently being executed. This interrupt is not "maskable," i.e., there is no way for the processor to prevent recognition of the interrupt. The NMI input responds to a negative transition. To interrupt the processor, the NMI input must go from high (> +2.4V) to low (< +0.4v). It can then stay low for an indefinite period without affecting the processor operation and without another interrupt. The processor will not detect another interrupt until this line goes high and then back to low. The NMI signal must be low for at least two clock cycles for the interrupt to be recognized, whereupon new program count vectors are fetched. 1.4.1.2.10 IRQ--Interrupt Request The interrupt request (IRQ) responds in much the same manner as NMI. However, this function can be enabled or disabled by the interrupt inhibit bit in the processor status register. As long as the I flag (inter- rupt inhibit flag) is a logic 1, the signal on the IRQ pin will not affect the processor. The IRQ pin is not edge-sensitive. Instead, the processor will be interrupted as long as the I flag is a logic "0" and the signal on the IRQ input is at GND. Because of this, the IRQ signal must be held low un- til it is recognized, i.e., until the processor completes the instruction currently being executed. If I is set when IRQ goes low, the interrupt will not be recognized until I is cleared through software control. To assure that the processor will not recognize the interrupt more than once, the I flag is set automatically during the last cycle before the processor begins executing the interrupt software, beginning with the fetch of program count. The final requirement is that the interrupt input must be cleared before the I flag is reset. If there is more than one active interrupt driving these two lines (OR'ed together), the recommended pro- cedure is to service and clear both interrupts before clearing the I flag. However, if the interrupts are cleared one at a time and the I flag is re- set after each, the processor will simply recognize any interrupts still active and will process them properly but more slowly because of the time required to return from one interrupt before recognizing the next. If the -38- procedure recommended above is followed, each interrupt will be recognized and processed only once. Figure 1.14 provides several examples of inter- rupts, microprocessor recognition of each interrupt (IRQ and NMI), and pro- cessor selection of interrupts during overlapped requests. Examples of Interrupt Recognition by MCS650X FIGURE 1.14 Each major event affecting the microprocessor is numbered in the figure with the corresponding explanations below. Event Number System Activity 1. Processor is executing from main program and IRQ goes to low state. 2. Upon completion of current instruction, the processor recognizes the interrupt, stores the contents of PC and P onto the stack and then sets I during the fetch of the interrupt vector. 3. After servicing the interrupt, IRQ should be reset before resetting the interrupt mask bit to avoid double interrupting. 4. Before the processor resumes normal main program exe- cution the interrupt mask bit will be reset low. 5. NMI now goes low, signalling a non-maskable interrupt request. -39- Event Number System Activity 6. The NMI interrupt is recognized and serviced in the same manner as IRQ. 7. The processor has resumed normal operation when NMI again goes low requesting an interrupt. 8. The interrupt mask bit is set high in response to the NMI request. 9. Here IRQ has gone low to signal an interrupt request. This request is ignored since the NMI interrupt is being serviced and the interrupt mask is set. 10. The interrupt mask bit is reset after servicing the NMI interrupt. 11. The processor is now able to recognize the IRQ signal, which is still low, and does so by setting the inter- rupt mask bit. 12. During the servicing of IRQ, NMI goes from high to low. The processor then completes the current instruction and abandons the IRQ interrupt to service NMI. NMI is serviced regardless of the state of the interrupt mask bit. 13. After completing the NMI interrupt routine, the pro- cessor will resume execution of the IRQ routine, even though IRQ has subsequently gone high. 1.4.1.2.11 RES--Reset The RES line is used to initialize the microprocessor from a power-down condition. During the power-up time this line is held low, and writing from the microprocessor is inhibited. When the line goes high, the microprocessor will delay 6 cycles and then fetch the new program count vec- tors from specific locations in memory (PCL from location FFFC and PCH from location FFFD). This is the start of the user's code. It should be assumed that any time the reset line has been pulled low and then high, the internal states of the machine are unknown and all registers must be re-initialized during the restart sequence. Timing for the reset sequence is shown in Figure 1.13. -40- 1.4.2 The MCS6502 1.4.2.1 Product Characteristics The MCS6502 is very similar to the MCS6501 described in detail in the previous section. It provides a full 16-pin address bus and therefore addresses a full 65,536 words (*) in memory. It also has the same data bus, R/W and RDY available on the MCS 6501. Figure 1.15 illustrates the pin configuration of the MCS6502. The differences between the two devices are as follows: 1. The MCS6502 has the oscillator and clock driver on-chip, thus eliminating the need for an external high-level two-phase clock generator. 2. The MCS6502 generates a SYNC signal instead of the bus avail- able (BA) signal. The SYNC signal is described in detail be- low. 3. Pin 5, corresponding to the MC6800 VMA signal, is not connec- ted. 4. The internal data bus enable function is connected directly to the phase two clock on the chip. Therefore pin 36 on the MCS6502 is not connected. 1.4.2.2 Device Timing--Requirements and Generation The MCS6501, in maintaining total bus compatibility with the MC6800 product family, requires a 5-volt two-phase clock. The MCS6502, however, can be used with an externally generated time base consisting of either a TTL level single-phase clock, crystal oscillator or RC network. Figures 1.16 and 1.17 show the configuration for setting the fre- quency of oscillations with a crystal or with an RC network. Figure 1.16 displays the crystal mode of operation in which the frequency of oscillation is set by the crystal operating in conjunction with the RC network. Figure 1.17 displays the same interconnects as in the crystal mode of time base generation, with the crystal removed from the -41- MCS6502 Pinout Designations FIGURE 1.15 -42- MCS6502 Parallel Mode Crystal Controlled Oscillator FIGURE 1.16a MCS6502 Series Mode Crystal Controlled Oscillator FIGURE 1.16b MCS6502 Time Base Generation - Crystal Controlled FIGURE 1.16 MCS6502 Time Base Generator - RC Network FIGURE 1.17 -43- circuit. Values of the feedback resistor, RF, and feedback capacitor, CF, will be different for the crystal mode versus the RC mode. while the de- tail specifications for values of RF and CF are found in the data sheet for the MCS6502, clock timing can be generated by use of combinations of RF in the range of 0 to 500K ohms and CF in the range of 2 to 12 pf. The reader is referred to the MCS6502 data sheet for a detailed description of the application of RC networks and crystal oscillators for generation of the time base in these modes of operation. The MCS6500 bus discipline described in Section 1.3.1 is appli- cable wherever the oscillator is located. For data transfers to be properly carried out between the processor and the various support chips in the sys- tems, the timing of the clocks controlling the internal processor opera- tions must be very close to that of the phase two clock out of pin 39 of the processor with no more than two TTL delays for clock buffering. It is important in systems which drive the clock generators with a TTL square wave that this input waveform not be used to control the peripheral chips unless care is taken to assure proper timing of the phase two clock being used in these support chips. 1.4.2.3 SYNC Signal In the MCS6502, a SYNC signal is provided to identify those cycles in which the processor is doing an OP CODE fetch. The SYNC line goes high during phase one of an OP CODE fetch and stays high for the remainder of that cycle. If the RDY line is pulled low during the phase one clock pulse in which the SYNC line went high, the processor will stop in its current state. It remains in that state until the RDY line goes high. In this manner, the SYNC signal can be used to control RDY to cause single-instruc- tion execution. This application is discussed in detail in Chapter 2. Figure 1.18 contains a timing diagram for this signal. 1.4.2.4 S.O.--Set Overflow This pin sets the overflow flag on a negative transition from TTL one to TTL zero. This is designed to work with a future I/O part and should not be used in normal applications unless the user has programmed for the fact the arithmetic operations also affect the overflow flag. -44- 1. During a microprocessor write cycle, R/W signal low, the SYNC pulse does not occur. 2. The R/W signal goes high to signal the beginning of a microprocessor read cycle. 3. At the beginning of the read cycle a SYNC pulse will be be generated. This pulse will last for one cycle time. The SYNC pulse indicates that the microprocessor is reading an OP CODE from the memory field. In this case the SYNC pulse is high for one cycle as the processor reads the OP CODE. 4. The processor outputs another SYNC pulse indicating it has completed the previous instruction and is fetching another OP CODE. In this case three more cycles are needed to complete this instruction before the next SYNC pulse is generated. The SYNC pulse is aperiodic in that its generation is a function of the program and the resultant lengths of the instructions and addressing modes. MCS6502 SYNC Signal FIGURE 1.18 -45- The operation of each function is exactly the same as on the MCS6502. | | | | | | Features | MCS6503 | MCS6504 | MCS6505 | | | | | | | | | | | | | | | | | Addressing | 4096 Bytes | 8192 Bytes | 4096 Bytes | | Capability | (AB00 - AB11) | (AB00 - AB12) | (AB00 - AB11) | | | | | | | | | | | | Interrupt | ___ ___ | ___ | ___ | | Request | IRQ, NMI | IRQ | IRQ | | Capability | | | | | | | | | | | | | | | | | | | | "Ready" Signal | -- | -- | RDY | | | | | | | | | | | | Timing | Single Phase | Single Phase | Single Phase | | Signals | TTL Level Ø0(IN), | TTL Level Ø0(IN), | TTL Level Ø0(IN), | | Required | or Crystal or RC | or Crystal or RC | or Crystal or RC | | | | | | | | | | | | Other Control | ___ | ___ | ___ | | Signals | RES, R/W | RES, R/W | RES, R/W | | | | | | Functional Features of MCS6503, MCS6504, MCS6505 FIGURE 1.19 -46- Figure 1.20 illustrates the pin designation for the three proces- sors, indicating the tradeoffs that exist between control signals and ad- dressing capability due to pinout constraints. Like the MCS6502, the 28- pin microprocessors also have the on-the-chip-oscillator and clock drivers. Figure 1.21 and 1.22 display the circuitry necessary to generate the time base in the crystal mode and RC network mode respectively. Specific de- tails on the value of feedback resistance, RF, and feedback capacitance, CF, can be found in the appropriate data sheet. -47- MCS6503, MCS6504, MCS6505 Pinout Designations FIGURE 1.20 -48- MCS6503,4,5 Parallel Mode Crystal Controlled Oscillator MCS6503,4,5 Series Mode Crystal Controlled Oscillator MCS6503, MCS6504, MCS6505 Time Base Generation Crystal Controlled FIGURE 1.21 MCS6503, MCS6504, MCS6505 Time Base Generator RC Network FIGURE 1.22 -49- 1.5 PERIPHERAL INTERFACE DEVICE - MCS6520 1.5.1 Introduction The MCS6520 is a direct pin for pin replacement for the Motorola MC6820 Peripheral Interface Adapter, the "PIA". As such, it meets all of the "PIA" electrical specifications and is totally hardware compatible with the MC6820. The MCS6520 is an I/O device which acts as an interface between the microprocessor and peripherals such as printers, displays, keyboards, etc. The prime function of the NG56520 is to respond to stimulus from each of the two worlds it is serving. On the one side, the MCS6520 is interfacing with peripherals via two eight-bit bi-directional peripheral data ports. On the other side, the device interfaces with the micropro- cessor through an eight-bit data bus; this is the same data bus discussed at length in Section 1.3.1. It is, therefore, simplest to view the basic function of the MCS6520 as in the block diagram of Figure 1.23. Basic MCS6520 Interface Diagram FIGURE 1.23 -50- In addition to the lines described above, the MCS6520 provides four interrupt input/peripheral control lines and the logic necessary for simple, effective control of peripheral interrupts. No external logic is required for interfacing the MCS650X microprocessor to most peripheral devices. The functional configuration of the MCS6520 is programmed by the microprocessor during systems initialization. Each of the peripheral data lines is programmed to act as an input or output and each of the four control/interrupt lines may be programmed for one of four possible control modes. This allows a high degree of flexibility in the overall operation of the interface. Some of the more important features of the MCS6520 are the following. * Compatibility with the MCS650X microprocessors. * Eight-bit bi-directional data bus for communication with the microprocessor. * Two eight-bit bi-directional ports for interface to peripherals. * Two programmable control registers. * Two programmable Data Direction Registers. * Four individually controlled interrupt input lines - two usable as peripheral control outputs. * Handshake control logic for input and output peripheral operation. * High impedance three-state and direct transistor drive peripheral lines. * Program controlled interrupt and interrupt mask capability. 1.5.2 Organization of the MCS6520 Figure 1.25 contains a block diagram of the MCS6520 showing the internal registers and data paths and the various inputs and outputs on the device. This section contains a general description of the internal organization of the device along with a discussion of how the various registers affect one another. The following sections discuss the details -51- MCS6520 Pinout Designations Peripheral Interface Adapter FIGURE 1.24 -52- MCS6520 Internal Architecture FIGURE 1.25 -53- of the inputs and outputs on the chip, along with a detailed discussion of the operation of each register. The final section discusses the MCS6520 from an operational viewpoint, describing the interaction of the register bits, input/output lines, etc. The MCS6520 is organized into two independent sections referred to as the "A Side" and the "B Side." Each section consists of a Control Regis- ter (CRA, CRB), Data Direction Register (DDRA, DDRB), Output Register (ORA, ORB), Interrupt Status Control and the buffer necessary to drive the Periph- eral Interface busses. 1.5.2.1 Data Input Register When the microprocessor writes data into the MCS6520, the data which appears on the data bus during the Phase Two clock pulse is latched into the Data Input Register. It is then transferred into one of six in- ternal registers of the MCS6520 after the trailing edge of Phase Two. This assures that the data on the peripheral output lines will not "glitch," i.e., the output lines will make smooth transitions from high to low or from low to high and the voltage will remain stable except when it is going to the opposite polarity. 1.5.2.2 Control Registers (CRA and CRB) Figure 1.29 illustrates the bit designation and functions in the Control Registers. The Control Registers allow the microprocessor to con- trol the operation of the interrupt lines (CA1, CA2, CB1, CB2), and periph- eral control lines (CA2, CB2). A single bit in each register controls the addressing of the Data Direction Registers (DDRA, DDRB) and the Output Reg- isters (ORA, ORB) discussed below. In addition, two bits (bit 6 and 7) are provided in each control register to indicate the status of the interrupt input lines (CA1, CA2, CBl, CB2). These interrupt status bits (IRQA, IRQB) are normally interrogated by the microprocessor during the interrupt serv- ice program to determine the source of an active interrupt. These are the interrupt lines which drive the interrupt input (IRQ, NMI) of the micro- processor. The other bits in CRA and CRB are described in the discussion of the interface to the peripheral device (Section 1.5.4). The various bits in the control registers will be accessed many times during a program to allow the processor to enable or disable inter- rupts) change operating modes, etc. as required by the peripheral device being controlled. -54- 1.5.2.3 Data Direction Registers (DDRA, DDRB) The Data Direction Registers allow the processor to program each line in the 8-bit Peripheral I/O port to act as either an input or an out- put. Each bit in DDRA controls the corresponding line in the Peripheral A port and each bit in DDRB controls the corresponding line in the Peripheral B port. Placing a "0" in the Data Direction Register causes the correspond- ing Peripheral I/O line to act as an input. A "1" causes it to act as an output. The Data Direction Registers are normally programmed only during the system initialization routine which is performed in response to a Reset signal. However, the contents of these registers can be altered during system operation. This allows very convenient control of some peripheral devices such as keyboards. 1.5.2.4 Peripheral Output Registers (ORA, ORB) The Peripheral Output Registers store the output data which ap- pears on the Peripheral I/O port. Writing an "0" into a bit in ORA causes the corresponding line on the Peripheral A port to go low (< 0.4v) if that line is programmed to act as an output. A "1" causes the corresponding output to go high. The lines of the Peripheral B port are controlled by ORB in the same manner. Addressing of these registers is discussed in Section 1.5.3.4. 1.5.2.5 Interrupt Status Control The four interrupt/peripheral control lines (CA1, CA2, CB1, CB2) are controlled by the Interrupt Status Control (A, B). This logic inter- prets the contents of the corresponding Control Register, detects active transitions on the interrupt inputs and performs those operations necessary to assure proper operation of these four peripheral interface lines. The operation of these lines is described in detail in Section 1.5.4.2. 1.5.2.6 Peripheral Interface Buffers (A, B) and Data Bus Buffers (DBB) The Buffers which drive the peripheral I/O ports and the data bus provide the current and voltage drive necessary to assure proper system operation and to meet the device specifications. -55- 1.5.3 Interface Between MCS6520 and the MCS650X Family of Microprocessors The MCS6520 interfaces to the microprocessor with an 8-bit bi-direc- tional data bus, 3 chip-select lines, 2 register-select lines, 2 interrupt request lines, read/write line, enable line and reset line. 1.5.3.1 Data Bus (D0-D7) The 8-bit, bi-directional data bus allows the transfer of data be- tween the microprocessor and the MCS6520. The data bus output drivers are 3-state devices that remain in the high impedance state except when the microprocessor reads data from the peripheral adapter. This data bus is the same as discussed in Section 1.3.1, "Bus Structure." 1.5.3.2 Enable (E) The Enable input is the only microprocessor interface timing input on the peripheral interface device. All data transfers into and out of the MCS6520 are controlled by this signal. In normal operation, this input should be connected to the phase two clock signal. In the case of the MCS6501, this is the 02 clock generated external to the microprocessor chip. For on-chip oscillator products (MCS6502, MCS6503, MCS6504 and MCS6505), the enable pulse becomes 02(OUT). 1.5.3.3 Read/Write (R/W) This signal is generated by the microprocessor to control the di- rection of data transfers on the data bus. A low (< 0.4v) on this line enables the input buffers (microprocessor Write) and data is transferred from the microprocessor to the MCS6520 under control of Enable input if the device has been chip-selected. A high on the R/W line allows the MCS6520 to transfer data to the data bus buffers. The data bus buffers are enabled when the proper chip-select and Enable signals are present. Figure 1.26 illustrates the Read/Write timing. 1.5.3.4 Chip Select Lines (CS1, CS2, CS3) These three inputs allow the microprocessor to select the proper peripheral interface device. CS1 and CS2 must be high and CS3 must be low for selection of the device. Data transfers are then performed under con- trol of the Enable and R/W signals. These lines are normally connected to the address lines on the microprocessor, either directly or through